The purpose of a cluster controller is to take high speed serial data coming from a host computer and multiplex it to one of a plurality of asynchronous serial ports. Similarly, the cluster controller must also be able to accept data from a plurality of low speed asynchronous serial ports and send it back to the host via a high speed (multiplexed) return serial path.
The cluster controller hardware commonly consists of a main processing unit (MPU) and a protocol controller that communicate through a common global random access memory (RAM) area. A commonly used protocol controller is manufactured by Motorola, Inc. and is referred to as a X.25 protocol controller (XPC).
The MPU transfers information directly to and from the host computer, while the protocol controller of the cluster controller may be linked to a remote cluster which controls a plurality of peripheral units. The common global RAM can be accessed by either the MPU or the protocol controller. To ensure proper functioning of the system, only the MPU or the protocol controller is granted access to the common global RAM at a single time.
The function of insuring access to the common global RAM is performed by a memory arbiter. Prior art memory arbiters granted access to either the protocol controller or the MPU at a single time. When the common global RAM was being utilized by one, the other had to wait for access. Since information flow from the MPU is often more vital to efficient operation of the system than information flow from the protocol controller, inefficient operation resulted when the protocol controller was accessing the common global RAM and the MPU made a request for access.